Embodiments of the invention relate generally to memory devices and more particularly to polling methods in memory devices.
An interleaved memory system may include a controller coupled to one or more memory devices. In an interleaved memory system, interleaved operations may be used by the controller to communicate with the one or more memory devices simultaneously. For example, during interleaved operations, the controller may issue a command to a first memory device and may communicate with a second memory device when the first memory device is busy executing the command issued by the controller.
An operational status of the memory device (whether the memory device is busy or ready) may be checked by the controller to determine completion of the command issued to the memory device. In a conventional method for checking the operational status of the memory device, a ready/busy pin of the memory device may be monitored by the controller. Upon execution of the command, the memory device informs the controller that the command has been executed by setting the ready/busy pin. However, in certain memory devices with pin restrictions, the controller is required to function without the ready/busy pins. Polling is another known method to check the operational status of a memory device which is adopted if the controller is required to function without the ready/busy pin. During polling, the operational status of the memory device is checked by polling a status register in the memory device. Polling is further explained in detail in conjunction with FIG. 1.
FIG. 1 is a block diagram illustrating an interleaved memory system 100 operating in a polling mode according to the prior art. The interleaved memory system 100 includes a controller 105 and one or more memory devices coupled to the controller including Device (A) 110 and Device (B) 115. Controller 105 further includes chip enable signal (A) line 120 and chip enable signal (B) line 125. Device (A) 110 and Device (B) 115 further include status register (A) 130 and status register (B) 135 respectively for storing a status of the respective memory devices 110 and 115.
Controller 105 sends commands to a memory device by asserting a chip enable signal to the memory device. The chip enable signal line is used to enable or disable the memory device. For example, controller 105 sends a read command to Device (A) 110 over the line 120 and an erase command to Device (B) 115 over the line 125 respectively. A status register in the device is used to store the status of the device. For example, status register (A) 130 stores the status of Device (A) 110 and status register (B) 135 stores the status of Device (B) 115 respectively. After sending the read command, controller 105 checks if Device (A) 110 is ready by polling the status register (A) 130. If Device (A) 110 is not ready, controller 105 polls that device 110 periodically for a fixed time interval until the device 110 is ready. For example, controller 105 may poll the device 110 after every 5 microseconds. Polling the device 110 periodically for a fixed time interval until the device 110 is ready may result in inefficient usage of the interface bandwidth. Moreover, devices may require different amounts of time to execute different commands. Hence, having a fixed time period to poll the device may result in inefficient use of the bandwidth of the memory system 100.
Once controller 105 detects that Device (A) 110 is ready, data from Device (A) 110 is read. After controller 105 completes reading the data, controller 105 may send another command to Device (A) 110. While communicating with Device (A) 110, controller 105 may proceed to poll status register (B) 135 in order to check if Device (B) 115 is ready. Therefore status register (B) 135 of Device (B) 115 may be polled while the controller is communicating with Device (A) 110. Such polling operations between data transfers also contribute to a net decrease in the effective bandwidth of the memory system 100.
Hence, there is a need for an efficient polling method. Further, there is also a need for maximizing bandwidth of a memory system.